In deep sub-micrometer semiconductor technology, due to soft errors and hard failures (e.g. Stuck Open/At or high/low resistive bridging), achieving a low value of Failures In Time (FIT) is a big challenge. Furthermore, applications in e.g. automotive, medical, petrochemical and space fields have high Safety Integrity Level (SIL) requirements. Thus, it is important to prevent any potentially dangerous effect of errors or at least to detect the errors and take proper reaction.
Typically, for safety features in semiconductor memory, two areas of investigation that are considered include data path fault coverage, and address and control path fault coverage. For example, in static random access memory (SRAM), the Error Correction Codes (ECC) bits are used to cover problems in cell arrays and input-output (I/O) parts. Thus, any single bit upset (SBU) due to soft error rate (SER) in cell array or I/O parts are fully covered by ECC. However, any SBU occurring in an address decoding path can lead to multi-bit failures, which are not completely detectable by the ECC or other means like built-in self-test (BIST) or scan chains, etc. in real-time applications of the memory in the product life-time.
In addition, dynamic logic is generally more prone to soft errors as the FIT rate for dynamic logic is much higher than the FIT rate for combinational logic. For example, in conventional latches (an example of which is shown in FIG. 1a), the positive feedback between nodes IN and OUT amplifies the effect of a radiation particle hit (e.g. an α-particle or a high-energy neutron) on any node and results in a flipping of the data stored. Thus, any SBU on one of the latches present in the memory can lead to a wrong operation. It has been reported that in the current technologies for small to medium size memory, instances of soft failure of dynamic logic (latches) contribute up to about 90% of the failures in real time.
Particularly, the latch on the internal clock of the memory (as shown in FIG. 1b) is somewhat different from all other latches used in the memory because it has a set and auto-reset behavior matched with the internal activity of the memory. The challenge on this type of latch is that the information stored is a timing sequence rather than a logic value (as in conventional latches). Possible scenarios in case of an SBU on the internal clock latch are summarized in Table 1 and illustrated in FIG. 1c. That is, when the memory is in an active state, the internal clock may not be triggered (e.g. cycle 106), may close early (e.g. cycle 108), or may be triggered between two cycles, i.e. twice in a single active cycle (e.g. cycle 102). When the memory is in an inactive state, the internal clock may be triggered erroneously once or more (e.g. cycle 104).
TABLE 1Failure mode of internal clockModedue to soft errorActiveNot triggeredClosed too earlyTriggered twice in single activecycleInactiveTriggered once or more
An existing approach for reducing SER in latches is shown in FIG. 2. In this approach, the latch circuit is modified by including a set of invertors by creating additional signals which stop the positive feedback of the latch in case only one of the nodes toggles due to soft error, thus reducing the FIT of the latch. However, the hard latch merely reduces the FIT rate but does not lower it down to zero, thus in case the latch flips, there is no detection and dangerous failures may occur. This approach penalizes the performance of the latch by introducing an extra load and cross resistance during the write step of the latch. Additionally, the logic becomes different from the classical latch and requires qualification and testing to quote the final FIT rate.
A need therefore exists to provide a circuit and method for detecting a single bit upset in a dynamic logic circuit that seeks to address at least one of the above problems, or to provide an alternative.